instruction execution
英 [ɪnˈstrʌkʃn ˌeksɪˈkjuːʃn]
美 [ɪnˈstrʌkʃn ˌeksɪˈkjuːʃn]
网络 指令执行
英英释义
noun
- (computer science) the process of carrying out an instruction by a computer
双语例句
- Composite electronic System is the hinge of the Pico-satellite, which undertakes the work of data processing, data storage, data transmission, Instruction code transmission and Instruction execution.
综合电子系统是皮卫星的数据和指令枢纽，承担皮卫星数据处理、数据存储、数据传输及指令收发、响应等重要任务，是皮卫星的核心组成部分。 - In the instruction execution pipeline stage, scalable pipeline technology was adopted to realize the video processing instruction.
为有效实现扩展指令，处理器执行级采用了可扩展流水级技术。 - Pipeline is dealing with instruction, including instruction decode, issue, and execution.
流水线正在处理指令，包括指令解码、发布和执行。 - As the core of SOC, CPU ′ s performance is mostly determined by instruction ′ s execution efficiency. Pipeline increases the instruction ′ s execution pace and improves the CPU ′ s performance.
作为SOC的核心，CPU的性能主要取决于指令的执行效率，而采用流水线方式大大增加了指令的执行速度，提高了CPU的性能。 - Research and Analysis of the Value Prediction and Instruction Reuse Techniques in Speculated Execution
推测执行中值预测与指令重用技术的研究与分析 - Static instruction scheduling decides the execution order of instructions and improves the instruction-level parallelism by reducing stall caused by dependences.
静态指令调度决定指令执行顺序，屏蔽指令间由于依赖关系而产生的延迟，从而提高了指令的并行度。 - In the traditional Cache, the Cache hit ratio is insured only by the address locality of memory reference instruction stream during program execution, it restricts the improvement of Cache hit ratio.
在传统的Cache中，仅仅依靠程序执行时访存指令流地址的局域性来保证较高的Cache命中率，使得Cache命中率的提高受到限制。 - This paper has discussed the relationship between the machine cycle and instruction execution time for superscalar RISC architecture, issuing multiple instructions in one machine cycle. Several new design features of superscalar RISC architecture with single execution unit and multiple function units have been analysed.
本文讨论超标量RISC结构中单周期发多条指令中周期和执行指令时间的相对关系，并分析了新型超标量RISC结构的实现方案，其中包括具有单个执行部件和多个执行部件的结构。 - The platform introduces two memory system structure, addressing mode simulation guarantees that not only the operand is correctly obtained, but also the instruction execution time is correctly calculated.
采用了两种存储器体系结构，寻址方式的模拟不仅保证了正确地确定操作数，而且能够正确统计指令执行时间。 - Based on the ( program counter) PC arbitrage strategy of multi-path execution, designing fetch instruction unit suit for selective dual path execution.
通过研究多路径执行中的PC仲裁机制，设计适合双路径执行结构的取指部件。